1. Field of the Invention
The present invention relates to an interface conversion circuit for a conversion of the frame structure of a first interface, such as a U-interface into a second interface (other interface).
2. Description of the Related Art
The connection between a station and terminal equipment in, for example, an ISDN (integrated services digital network) is shown in FIG. 7. In FIG. 7, the reference numeral 101 indicates a station and the reference numeral 102 indicates terminal equipment. A network terminating unit (OCU) 103 in the station 101 and a subscriber terminating unit (DSU) 104 in the terminal equipment 102 are connected to each other by means of a subscriber's line 105. Furthermore, a plurality of terminals (TE) 106 are connected to the subscriber terminating unit 104. The subscriber terminating unit 104 referred to herein is defined in TI. 601-1988 of ANSI (American National Standard Institute).
Note that the subscriber terminating unit 104 and subscriber's line 105 will be referred to as an "U-interface" hereinafter while the terminal 106 of the subscriber terminating unit 104 as a "S/T-interface".
The subscriber terminating unit 104 is provided with a U-interface circuit 107 and a S/T-interface circuit 108 as shown in FIG. 8.
The U-interface circuit 107 converts the frame construction of the U-interface into another interface (will be referred to as "A-interface" hereinafter), and the S/T-interface circuit 108 converts the frame structure of the A-interface into an S/T-interface.
A super frame [see FIG. 12 (a)] consisting of eight basic frames has to be used for the flow of information on the U-interface as stipulated in TI. 601-1988 of ANSI.
In FIG. 12 (a), ISW are bits for an inversion-synchronous word, SW are bits for a synchronous word, 2B+D are bits for a customer data channel and M are bits for a maintenance channel. The basic-frame period is 1.5 ms (millisecond). The super frame has eight basic frames, so its period is 12 ms.
As shown in FIG. 12 (b), the A-interface has a super frame structure consisting of 96 frames (A1, A2, ..., A96). The frame period is 125 .mu.s (microsecond). Since the super frame consists of 96 frames, its period is 12 ms.
In the case of a conversion from a U-interface into an A-interface, the scale of a latch circuit in a MUX (multiplexer) can be minimized by establishing a certain phase relation between the super frames of the two interfaces.
FIG. 9 is a block diagram of a conventional U-interface circuit. As shown, the U-interface circuit comprises a reception timing signal generator (RTIM) 201 and an A-interface timing signal generator (ATIM) 202.
A block diagram showing the reception timing signal generator 201 used in the conventional interface conversion circuit is shown in FIG. 10. Receiving a 160 kHz reception clock R160K (produced by a frequency division of a signal generated by DPLL and which is synchronous with 80 kHz signal of the U-interface) and a reception counter output signal (output signal from a reception counter that receives the 160 kHz reception clock R160K), the reception timing signal generator 201 produces a window signal WND having a predetermined time duration of 20 bits, which indicates the frame top position of the A-interface. For this purpose of producing the window signal WND, the reception timing signal generator 201 has a decoder 203 and a JK flip-flop 204.
The decoder 203 receives a reception counter outer signal and produces signals indicative of an a-bit position and (a+20) -bit position, respectively, of the super frame on the U-interface. The JK flip-flop 204 is provided to produce, from the signal from the decoder 203 and the 160 kHz reception clock R160K, a window signal WND having a predetermined time duration of 20 bits indicative of the frame top position on the A-interface.
Since the signal speed of the U-interface is 160 kbps (kilobits per sec) in this case, transmission of 20 bits over the U-interface takes 125 .mu.s. Therefore, the window signal WND has a time duration of 20 bits (125 .mu.s) on the U-interface.
The A-interface timing signal generator 202 as shown in FIG. 11 is adapted to determine the frame top position in the A-interface based on the window signal WND from the reception timing signal generator 201, an A-interface frame clock MTC and an A-interface bit clock C. To this end, the A-interface timing signal generator 202 comprises a differentiation circuit 205 and an A-interface counter load signal output unit 206.
The differentiation circuit 205 comprises two D flip-flops. Receiving the A-interface frame clock MTC and an A-interface bit clock C, this circuit 205 takes out one bit from the top of the A-interface frame clock MTC.
The A-interface counter lock signal output unit 206 has two AND gates (one of which receives an inversion output from the differentiation circuit 205). The output unit 206 ANDs the A-interface frame clock MTC with the inversion output from the output-stage flip-flop of the differentiation circuit 205 and also ANDS this AND output with the window signal WND to produce an A-interface counter load signal.
Because of the above-mentioned arrangement, a window signal WND having a time duration of 20 bits (125 .mu.s) is produced in a position on the U-interface to which it is desired to bring the top of the super frame of the A-interface as shown in FIG. 13 (a) to (d), thereby taking as the top of the super frame the top of an A-interface frame clock MTC having a time period for which the window signal WND is "H". Namely, it is necessary that the top A1 of the super frame should always be completely synchronous with the frame clock MTC.
It should be noted here that there is no certain phase relation between the U-interface reception clock and A-interface frame clock. Namely, "tp" in FIG. 13 can take an arbitrary value ranging from 0 to 125 .mu.s and the value of tp depends mainly on the timing of initial lead-in. If the tp value is constant during communications, the phase difference between both the U-interface and A-interface super frames will always be constant.
Actually, however, the tp value varies little by little because of the relative jitter between the U-interface reception clock and an A-interface frame clock.
Assume here that the variation of the tp value of one super frame is .DELTA.tp and the period of an A-interface bit clock is T.sub.B. Since there is generally the following relation between the variation .DELTA.tp and period T.sub.B EQU .DELTA.tp&lt;&lt;T.sub.B ... (1)
the above jitter can be absorbed.
However, even if the equation (1) is met, the frame position may possibly be shifted one frame back or ahead when the tp value is approximate to 0 or 125 .mu.s.
FIG. 14 (a) to (f) show that when the tp value is very near 0 .mu.s, the A-interface frame clock MTC rises before the window signal WND in the next super frame, so that the frame position is shifted one frame back. It means that a blank will occur between the last data A96 in the preceding super frame and the first data A in the following super frame.
FIG. 15 (a) to (f) show that when the tp value is very near 125 .mu.s, the A-interface frame clock MTC rises before the window signal WND does in the next super frame so that the frame position is shifted one frame ahead. Namely, if the frame clock MTC rises near the fall of the window signal WND, when the preceding frame clock enters the window signal WND because of a jitter or the like, the last data A96 in the preceding super frame will be erased.
Therefore, if the window signal WND synchronous with the received signal is in a certain phase relation with the A-interface frame clock MTC in the conventional circuit, the relative jitter between clocks of both interfaces cannot be absorbed.